The present invention relates to a semiconductor device including transistors and connection between the transistors for constituting an LSI with high integration and a decreased area.
With the recent development of a semiconductor device with high integration and high performance, there are increasing demands for more refinement of the semiconductor device. The improvement of the conventional techniques cannot follow these demands, and novel techniques are unavoidably introduced in some technical fields. For example, as a method of forming an isolation, the LOCOS isolation method is conventionally adopted in view of its simpleness and low cost. Recently, however, it is considered that a trench buried type isolation (hereinafter referred to as the trench isolation) is more advantageous for manufacturing a refined semiconductor device.
Specifically, in the LOCOS isolation method, since selective oxidation is conducted, the so-called bird's beak occurs in the boundary with a mask for preventing the oxidation. As a result, the dimension of a transistor is changed because an insulating film of the isolation invades a transistor region against the actually designed mask dimension. This dimensional change is unallowable in the refinement of a semiconductor device after the 0.5 μm generation. Therefore, even in the mass-production techniques, the isolation forming method has started to be changed to the trench isolation method in which the dimensional change is very small. For example, IBM corporation has introduced the trench isolation structure as a 0.5 μm CMOS process for the mass-production of an MPU (IBM Journal of Research and Development, VOL. 39, No. 1/2, 1995, pp. 33–42).
Furthermore, in a semiconductor device mounting elements such as a MOSFET in an active area surrounded with an isolation, an insulating film is deposited on the active area, the isolation and a gate electrode, and a contact hole is formed by partly exposing the insulating film for connection between the active area and an interconnection member on a layer above the insulating film. This structure is known as a very common structure for the semiconductor device.
FIG. 17 is a sectional view for showing the structure of a conventional semiconductor device. In FIG. 17, a reference numeral 1 denotes a silicon substrate, a reference numeral 2b denotes an isolation with a trench isolation structure which is made of a silicon oxide film and whose top surface is flattened so as to be at the same level as the top surface of the silicon substrate 1, a reference numeral 3 denotes a gate oxide film made of a silicon oxide film, a reference numeral 4a denotes a polysilicon electrode working as a gate electrode, a reference numeral 4b denotes a polysilicon interconnection formed simultaneously with the polysilicon electrode 4a, a reference numeral 6 denotes a low-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a low concentration, a reference numeral 7a denotes an electrode sidewall, a reference numeral 7b denotes an interconnection sidewall, a reference numeral 8 denotes a high-concentration source/drain region formed by doping the silicon substrate with an n-type impurity at a high concentration, a reference numeral 12 denotes an insulating film made of a silicon oxide film, and a reference numeral 13 denotes a local interconnection made of a polysilicon film formed on the insulating film 12.
The local interconnection 13 is also filled within a connection hole 14 formed in a part of the insulating film 12, so as to be contacted with the source/drain region in the active area through the connection hole 14. In this case, the connection hole 14 is formed apart from the isolation 2b by a predetermined distance. In other words, in the conventional layout rule for such a semiconductor device, there is a rule that the edge of a connection hole is previously located away from the boundary between the active area and the isolation region so as to prevent a part of the connection hole 14 from stretching over the isolation 2b even when a mask alignment shift is caused in photolithography (this distance between the connection hole and the isolation is designated as an alignment margin).
However, in the structure of the semiconductor device as shown in FIG. 17, there arise problems in the attempts to further improve the integration for the following reason:
A distance La between the polysilicon electrode 4a and the isolation 2b is estimated as an index of the integration. In order to prevent the connection hole 14 from interfering the isolation 2b as described above, the distance La is required to be 1.2 μm, namely, the sum of the diameter of the connection hole 14, that is, 0.5 μm, the width of the electrode sidewall 7a, that is, 0.1 μm, the alignment margin from the polysilicon electrode 4a, that is, 0.3 μm, and the alignment margin from the isolation 2b, that is, 0.3 μm. A connection hole has attained a more and more refined diameter with the development of processing techniques, and also a gate length has been decreased as small as 0.3 μm or less. Still, the alignment margin in consideration of the mask alignment shift in the photolithography is required to be approximately 0.3 μm. Accordingly, as the gate length and the connection hole diameter are more refined, the proportion of the alignment margin is increased. This alignment margin has become an obstacle to the high integration.
Therefore, attempts have been made to form the connection hole 14 without considering the alignment margin in view of the alignment shift in the photolithography. Manufacturing procedures adopted in such a case will now be described by exemplifying an n-channel MOSFET referring to FIGS. 18(a) through 18(c).
First, as is shown in FIG. 18(a), after forming an isolation 2b having the trench structure in a silicon substrate 1 doped with a p-type impurity (or p-type well), etch back or the like is conducted for flattening so as to place the surfaces of the isolation 2b and the silicon substrate 1 at the same level. In an active area surrounded with the isolation 2b, a gate oxide film 3, a polysilicon electrode 4a serving as a gate electrode, an electrode sidewall 7a, a low-concentration source/drain region 6 and a high-concentration source/drain region 8 are formed. On the isolation 2b are disposed a polysilicon interconnection 4b formed simultaneously with the polysilicon electrode 4a and an interconnection sidewall 7b. At this point, the top surface of the high-concentration source/drain region 8 in the active area is placed at the same level as the top surface of the isolation 2b. Then, an insulating film 12 of a silicon oxide film is formed on the entire top surface of the substrate.
Next, as is shown in FIG. 18(b), a resist film 25a used as a mask for forming a connection hole is formed on the insulating film 12, and the connection hole 14 is formed by, for example, dry etching.
Then, as is shown in FIG. 18(c), the resist film 25a is removed, and a polysilicon film is deposited on the insulating film 12 and within the connection hole 14. The polysilicon film is then made into a desired pattern, thereby forming a local interconnection 13.
At this point, in the case where the alignment margin in view of the mask alignment shift in the formation of the connection hole 14 is not considered in estimating the distance La between the polysilicon electrode 4a and the isolation 2b, a part of the isolation 2b is included in the connection hole 14 when the exposing area of the resist film 25a is shifted toward the isolation 2b due to the mask alignment shift in the photolithography. Through over-etch in conducting the dry etching of the insulating film 12, although the high-concentration source/drain region 8 made of the silicon substrate is not largely etched because of its small etching rate, the part of the isolation 2b included in the connection hole 14 is selectively removed, resulting in forming a recess 40 in part of the connection hole 14. When the recess 40 in the connection hole 14 has a depth exceeding a given proportion to the depth of the high-concentration source/drain region 8, junction voltage resistance can be decreased and a junction leakage current can be increased because the concentration of the impurity in the high-concentration source/drain region 8 is low at that depth.
In order to prevent these phenomena, it is necessary to provide a predetermined alignment margin as is shown in the structure of FIG. 17 so as to prevent the connection hole 14 from interfering the isolation 2b even when the alignment shift is caused in the lithography. In this manner, in the conventional layout rule for a semiconductor device, an alignment margin in view of the mask alignment shift in the photolithography is unavoidably provided.
Furthermore, a distance between the polysilicon electrode 4a and the connection hole 14 is also required to be provided with an alignment margin. Otherwise, the connection hole 14 can interfere the polysilicon electrode 4a due to the fluctuation caused in the manufacturing procedures, resulting in causing electric short-circuit between an upper layer interconnection buried in the connection hole and the gate electrode.
As described above, it is necessary to provide the connection hole 14 with margins for preventing the interference with other elements around the connection hole, which has become a large obstacle to the high integration of an LSI.
Also in the case where a semiconductor device having the so-called salicide structure is manufactured, the following problems are caused due to a recess formed in the isolation:
FIG. 19 is a sectional view for showing an example of a semiconductor device including the conventional trench isolation and a MOSFET having the salicide structure. As is shown in FIG. 19, a trench isolation 105a is formed in a silicon substrate 101. In an active area surrounded with the isolation 105a, a gate insulating film 103a, a gate electrode 107a, and electrode sidewalls 108a on both side surfaces of the gate electrode 107a are formed. Also in the active area, a low-concentration source/drain region 106a and a high-concentration source/drain region 106b are formed on both sides of the gate electrode 107a. A channel stop region 115 is formed below the isolation 105a. Furthermore, in areas of the silicon substrate 101 excluding the isolation 105a and the active area, a gate interconnection 107b made of the same polysilicon film as that for the gate electrode 107a is formed with a gate insulating film 103b sandwiched, and the gate interconnection 107b is provided with interconnection sidewalls 108b on its both side surfaces. On the gate electrode 107a, the gate interconnection 107b and the high-concentration source/drain region 106b, an upper gate electrode 109a, an upper gate interconnection 109b and a source/drain electrode 109c each made of silicide are respectively formed. Furthermore, this semiconductor device includes an interlayer insulating film 111 made of a silicon oxide film, a metallic interconnection 112 formed on the interlayer insulating film 111, and a contact member 113 (buried conductive layer) filled in a connection hole formed in the interlayer insulating film 111 for connecting the metallic interconnection 112 with the source/drain electrode 109c. 
Now, the manufacturing procedures for the semiconductor device including the conventional trench isolation and the MOSFET with the salicide structure shown in FIG. 19 will be described referring to FIGS. 20(a) through 20(e).
First, as is shown in FIG. 20(a), a silicon oxide film 116 and a silicon nitride film 117 are successively deposited on a silicon substrate 101, and a resist film 120 for exposing an isolation region and masking a transistor region is formed on the silicon nitride film 117. Then, by using the resist film 120 as a mask, etching is conducted, so as to selectively remove the silicon nitride film 116 and the silicon oxide film 117, and further etch the silicon substrate 101, thereby forming a trench 104. Then, impurity ions are injected into the bottom of the trench 104, thereby forming a channel stop region 115.
Then, as is shown in FIG. 20(b), a silicon oxide film (not shown) is deposited, and the entire top surface is flattened until the surface of the silicon nitride film 117 is exposed. Through this procedure, a trench isolation 105a made of the silicon oxide film filled in the trench 104 is formed in the isolation region Reiso.
Next, as is shown in FIG. 20(c), after the silicon nitride film 117 and the silicon oxide film 116 are removed, a gate oxide film 103 is formed on the silicon substrate 101, and a polysilicon film 107 is deposited thereon. Then, a photoresist film 121 for exposing areas excluding a region for forming a gate is formed on the polysilicon film 107.
Then, as is shown in FIG. 20(d), by using the photoresist film 121 as a mask, dry etching is conducted, thereby selectively removing the polysilicon film 107 and the gate oxide film 103. Thus, a gate electrode 107a of the MOSFET in the transistor region Refet and a gate interconnection 107b stretching over the isolation 105a and the silicon substrate 101 are formed. After removing the photoresist film 121, impurity ions are injected into the silicon substrate 101 by using the gate electrode 107a as a mask, thereby forming a low-concentration source/drain region 106a. Then, a silicon oxide film 108 is deposited on the entire top surface of the substrate.
Next, as is shown in FIG. 20(e), the silicon oxide film 108 is anisotropically dry-etched, thereby forming electrode sidewalls 108a and interconnection sidewalls 108b on both side surfaces of the gate electrode 107a and the gate interconnection 107b, respectively. At this point, the gate oxide film 103 below the silicon oxide film 108 is simultaneously removed, and the gate oxide film 103 below the gate electrode 107a alone remains. Then, impurity ions are diagonally injected by using the gate electrode 107a and the electrode sidewalls 108a as masks, thereby forming a high-concentration source/drain region 106b. Then, after a Ti film is deposited on the entire top surface, high temperature annealing is conducted, thereby causing a reaction between the Ti film and the components made of silicon directly in contact with the Ti film. Thus, an upper gate electrode 109a, an upper gate interconnection 109b and a source/drain electrode 109c made of silicide are formed. The procedures to be conducted thereafter are omitted, but the semiconductor device including the MOSFET having the structure as shown in FIG. 19 can be ultimately manufactured. In FIG. 19, the metallic interconnection 112 is formed on the interlayer insulating film 111, and the metallic interconnection 112 is connected with the source/drain electrode 109c through the contact member 113 including a W plug and the like filled in the contact hole.
When the aforementioned trench isolation structure is adopted, the dimensional change of the source/drain region can be suppressed because the bird's beak, that is, the oxide film invasion of an active area, which is caused in the LOCOS method where a thick silicon oxide film is formed by thermal oxidation, can be avoided. Furthermore, in the procedure shown in FIG. 20(c), the surfaces of the isolation 105a and the silicon substrate 101 in the transistor region Refet are placed at the same level.
In such a semiconductor device having the trench type isolation, however, there arise the following problems:
When the procedures proceed from the state shown in FIG. 20(d) to the state shown in FIG. 20(e), the silicon oxide film 108 is anisotropically etched so as to form the sidewalls 108a and 108b. At this point, over-etch is required. Through this over-etch, the surface of the isolation 105a is removed by some depth.
FIGS. 21(a) and 21(b) are enlarged sectional views around the boundary between the high-concentration source/drain region 106b and the isolation 105a after this over-etch.
As is shown in FIG. 21(a), between the procedures shown in FIGS. 20(d) and 20(e), the impurity ions are diagonally injected so as to form the high-concentration source/drain region 106b. Through this ion injection, the high-concentration source/drain region 106b is formed also below the edge of the isolation 105a because the isolation 105a is previously etched by some depth. Accordingly, the high-concentration source/drain region 106b is brought closer to the channel stop region 115, resulting in causing the problems of degradation of the junction voltage resistance and increase of the junction leakage current.
In addition, as is shown in FIG. 21(b), in the case where the Ti film or the like is deposited on the high-concentration source/drain region 106b so as to obtain the silicide layer through the reaction with the silicon below, the thus formed silicide layer can invade the interface between the silicon substrate 101 and the isolation 105a with ease. As a result, a short-circuit current can be caused between the source/drain electrode 109c made of silicide and the channel stop region 115.